The present invention relates in general to integrated circuits and, more particularly, to wafer level testing of multiple wafers for the selection of system components for a match set using wafer interposers to couple the wafers to a testing apparatus.
Modern electronic devices utilize semiconductor chips, commonly referred to as integrated circuits, which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect the chips with other elements of the circuit. Such substrates may then be secured to an external circuit board or chassis.
The size of the chips and substrate assembly is a major go concern in modern electronic product design. The size of each subassembly influences the size of the overall electronic device. Moreover, the size of each subassembly controls the required distance between each chip and between chips and other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limit the speed of operation of the device. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays, can permit faster operations.
One approach for improving overall system performance is through the use of matched sets. For example, several identical or dissimilar components that have been identified by the individual testing phase of component processing to have certain performance tracking characteristics may be assembled together as a matched set. The components of such a matched sets are frequently attached to a single substrate in close proximity to one another. This strategy improves performance compared to conventional or non-optimized systems by reducing the overall space needed to accommodate the chips and by, among other things, shortening the distance between chips. Specifically, interconnect inductance and signal transmission delays are all reduced.
One type of matched set includes a collection of identical components which have been identified to meet specific system performance requirements. For example, radio frequency (RF) systems often employ identical filters, switches, power dividers, mixers and high frequency amplifiers. Typically, each of the identical components has been extensively tested individually prior to inclusion in this type of system. The individual characterization tests for a filter, for instance, might measure insertion loss and phase shift as a function of frequency, input power and temperature. These multi-dimensional arrays of data are then compared to each other to identify individual components that perform within acceptable limits relative to each other. Components that are found to exhibit similar behavior under the various input stimuli will constitute a matched set of identical devices. Conversely, components that are found to exhibit dissimilar behavior under the various input stimuli, for example, the gain of one component having a negative slope over temperature while the gain of another component having a positive slope over temperature, will constitute a mismatch of components that will not be placed in a chip collection.
Another type of matched set includes components of different device types that are combined such that the aggregate, cascaded performance meets system specifications. Mixed signal systems, for example, often utilize digital-to-analog (DAC) converters along with operational amplifiers (OpAmp) to process data. The performance of a product can often be improved by pairing a DAC with an OpAmp of similar performance. That is, the input characteristics of the OpAmp are optimized to match the output characteristics of the DAC. As in the case of the matched set of identical components described above, the component of a matched set of different components are also identified by comparing multi-dimensional arrays of data to each other to identify individual components that perform within acceptable limits relative to each other. Components that are found to exhibit similar behavior under the various input stimuli will form a matched set of different components while components that are found to exhibit dissimilar behavior under the various input stimuli are not placed in a chip collection due to the mismatch.
It has been found, however, the certain mismatches are not identified when the components are tested individually. In fact, certain mismatches are not identified until the entire chip collection is assembled and the components are tested together for the first time. As such, some chip collections must be disassembled so that the valuable components may be, for example, packaged as individual components, while other chip collections are simple discarded.
Therefore, a need has arisen for an improved method for selection of system components for a matched set. A need has also arisen for such a method that does not require elaborate data reduction of test results from individually tested components. Additionally, a need has arisen for such a method that allows for testing of the individual components together prior to the assembly of the matched set.
The present invention disclosed herein provides a chip collection, known as a matched set, that maximizes system performance by selecting well matched integrated circuit chips for assembly together into the matched set. The present invention achieves this result by allowing for testing of the various integrated circuit chips together prior to the assembly of the matched set. This testing is preformed by simultaneously connecting multiple wafer-interposer assemblies, each including a wafer level interposer and a wafer, to a testing apparatus. Thus, all of the chips to be included in the matched set may be tested together. After testing, these wafer-interposer assemblies are diced into a plurality of chip assemblies that are assembled into the matched set.
In its broadest form, the present invention provides for the attachment of two semiconductor wafers each having a plurality of integrated circuit chips thereon to a pair of interposers for testing of the integrated circuit chips. The integrated circuit chips of the first wafer may be of the same type as the integrated circuit chips of the second wafer, such as DRAM chips. Alternatively, the integrated circuit chips of the first wafer may be of a different type from the integrated circuit chips of the second wafer. For example, the integrated circuit chips of the first wafer may be amplifiers while the integrated circuit chips of the second wafer may be controllers. Likewise, the integrated circuit chips of the first wafer may carry the same type of signal as the integrated circuit chips of the second wafer, such as analog signals for an amplifier. Alternatively, the integrated circuit chips of the first wafer may carry a different type of signal than the integrated circuit chips of the second wafer. For example, the integrated circuit chips of the first wafer may be mixers that carry RF signals while the integrated circuit chips of the second wafer may be DSPs that carry digital signals.
Prior to testing, the two wafers are electrically and mechanically coupling to the two interposers such that the wafer-interposer assemblies may be connected to a testing apparatus. The testing may include performance tests over a range of temperatures, testing for leakage currents, testing for offset voltages and the like to determine which integrated circuit chips from the first wafer could be included in a matched set with particular integrated circuit chips from the second wafer to achieve optimum performance. Likewise, the testing may include grading of the integrated circuit chips of the first wafer and the second wafer for speed or other performance characteristics such that the integrated circuit chips of the first wafer that receive a particular grade are matched with integrated circuit chips from the second wafer having a similar grade. Additionally, the testing may include testing for non-conformance wherein certain integrated circuit chips of the first wafer may not be matched with any integrated circuit chips of the second wafer.
Once testing is complete, the wafer-interposer assemblies may be diced into a plurality of chip assemblies having chips of the first wafer and a plurality of chip assemblies having chips of the second wafer. One of the chip assemblies having a chip from the first wafer may them be matched with one of the chip assemblies having a chip from the second wafer, for inclusion in a matched set. This selection is based upon the results of the testing of the integrated circuit chips of the first wafer and the integrated circuit chips of the second wafer. Alternatively, more than one of the chip assemblies having chips from the first wafer may be matched with one or more chip assemblies having chips from the second wafer for inclusion in a matched set.
Using this process, all or substantially all of the integrated circuit chips from one wafer may be matched with one or more of the integrated circuit chips of a second wafer based upon the desired performance characteristics of the matched set that will contain these devices. By performing the testing prior to assembly of the matched set, the performance characteristics of each of the matched sets assembled using integrated circuit chips of the first and second wafers are enhanced as is the overall performance of the entire lot of matched set devices.